In a NAND flash memory, the data stored in a cell is read out through the page buffer. The page buffer also serves program verification and erase verification that function as a read operation. Page buffers appear in a variety of designs. FIG. 1 is one design of page buffer, which is published in “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme”, IEEE Journal of Solid-State-Circuit, Vol. 30, No. 11, p. 1149-1155, November 1995. The read operation is described as follows. First, the word line (not shown) switches to logic low and thus no current occurs in the cell. Then, the bit line BL is discharged to ground by turning on NMOS 102 and 103. Next, the bit line BL is charged to VCC by turning off NMOS 103 and 104 and turning on PMOS 101. The page buffer uses a mirrored current provided by a PMOS 101 noted as a current load to pull up the bit line BL. The mirrored current is compared with the accessed cell current on the bit line BL and thus defines the bit line voltage. If the accessed cell is in low threshold voltage (i.e., erase state), it will be turned on by the word line and has an electrical current larger than the mirrored current during read or verification. Consequently, the bit line BL will be discharged gradually and NMOS 105 is turned off. If the accessed cell is in high threshold voltage (i.e., program state), the voltage on the word line cannot turn on this cell. The mirror current will pull the bit line BL in high voltage state and NMOS 105 will be turned on. After a period of time, namely the signal development time, the cell state is sent to the latch in the page buffer by activating a “READ ” pulse to turn on NMOS 106, and thus the data stored in the cell is transferred to the page buffer.
U.S. Pat. No. 6,671,204 does not use the mirrored current scheme but discloses a page buffer as shown in FIG. 2 instead, in which a bit line BLE is selected for reading and another bit line BLO used as a shielding bit line. FIG. 3 illustrates a timing diagram with reference to the schematic shown in FIG. 2. In Region 2 of FIG. 3, the bit lines BLE and BLO are discharged to ground first by turning on NMOS 201 and 203 in connection with grounded VIRPWR. The node SO is also discharged by turning on NMOS transistors 202 and 204. Then, Region 3 is active, during which BLSHFO switches to logic low, the word line WL is turned on, BLSHFE is biased at about 2.0V and PLOAD is active low. The node SO is pulled to VCC and charges up the bit line BLE to 2.0V-VTH, where VTH is the threshold voltage of NMOS 204 and is typically about 1V. The 2.0V bias and the threshold voltage on NMOS 204 clamp the voltage level of the bit line BLE. When the voltage level of the bit line BLE is stabilized, Region 4 is active and BLSHFE is pulled to ground level to turn off NMOS 204, and namely the signal development starts on the bit line BLE. The bit line BLE will be discharged to a lower level if the accessed cell has a low threshold voltage and is turned on. In contrast, if the accessed cell has a high threshold voltage, it will not be turned on and the bit line BLE keeps the pre-charge voltage level. After the signal development time, Region 5 is active. NMOS 204 is turned on again but the voltage level of BLSHFE is around 1.3V only. This is used to sense the voltage level of the bit line BLE with respect to the node SO. The node SO with VCC level will be discharged to the bit line BLE if the bit line BLE is at low level, and NMOS 204 will be turned on. While the node SO remains at VCC level and NMOS 204 is off if the accessed cell has high threshold voltage or the bit line BLE is at 1V. The signal of the node SO will be sent to a left register 205 by activating a PBLCHM pulse signal. In this conventional scheme, a timer is required to control the activation of the PBLCHM signal. The timer will count up to a pre-determined time period, so as to ensure that the signal PLOAD goes high in Region 4. In Region 6, all bit lines and the node SO are discharged to ground again. In Region 7, all control signals of the page buffer are disabled.
U.S. Pat. No. 6,925,005 discloses a sensing method to track the memory cell position in bit line direction and word line direction. The cell array is divided into many regions. Each region has a reference bit line to control the sensing timing for this region. The reference bit line has a reference cell to each crossed word line. That is, the reference bit lines have the same connection as normal bit lines. However, this method will result in difficulty in efficiently adjusting the threshold voltages for so many reference cells. Another concern is about disturbance/drifting of the threshold voltage of the reference cell, which is caused by the adjacent normal bit lines and reference bit lines. That is, when the normal cells are programmed, the associated word lines go high and will affect the threshold voltages of the reference cells. Similarly, the drifting of the threshold voltages of the reference cells also occurs during the erase operation.
U.S. Pat. No. 6,304,486 uses a single reference bit line and a reference cell at each intersection of word lines and this single reference bit line. It means each page has a reference cell. When this reference cell passes erase verification, it will initiate the verification on normal cells. Additionally, when this reference cell passes program verification, it will initiate the program verification on normal cells. However, if one of the reference cells fails, the corresponding word line fails to access normal cells. Another concern is the reliability of the reference cells that degrade due to repeated program and erase operations with the normal cells.
U.S. Pat. No. 5,754,475, applied on multiple-level cell design, uses multiple reference bit lines. Each reference bit line has a reference cell at each intersection of word lines and reference bit line. The reference cells on each reference bit line have a pre-tuned threshold voltage during production. However, in this design, tuning the threshold voltages of the reference cells is time-consuming, increasing production cost drastically and therefore not feasible. For example, there are 32,000 word lines in a 1 Gb NAND flash memory and thus there are 96,000 reference cells in need of threshold voltage adjustment. Another concern is about disturbance/drifting of the threshold voltage of the reference cell, which is caused by the adjacent normal bit lines and reference bit lines.
In each of the conventional schemes mentioned above, a timer is required to control the activation of the control signal, e.g., the signal PBLCHM of FIG. 2, to start the operation of read or program verification; also, the timer will count up to a pre-determined time period, so as to ensure that the PLOAD signal goes high in Region 4 of FIG. 3. In practice, the sensing timing controlled by the timer is determined by simulation and then is implemented by a logic circuit. Thus, the control of the sensing timing by the timer may fail if the RC (product of resistance and capacitance) of the bit line changes due to variation of the fabrication process.